CovR: Coverage-Aware Hardware Verification via Reasoning-Guided Reinforcement Learning

Excerpt

arXiv:2609.19189v1 Announce Type: cross Abstract: Design verification remains one of the most resource-intensive stages of hardware development, often consuming up to 70% of the total design effort. While recent work has explored using Large Language Models (LLMs) to automate testbench generation, most existing approaches focus narrowly on functional correctness, overlooking the critical aspect of coverage quality. To bridge this gap, we present CovR, an agentic framework for automated testbench