Validity-Preserving Hierarchical RL for Joint Routing and Switch Placement in EDA

Excerpt

arXiv:2609.39749v1 Announce Type: new Abstract: Routing and switch placement are fundamental combinatorial optimization problems in chip design, requiring the joint optimization of routing topology and physical placement under strict structural, geometric and logical constraints. Existing approaches typically rely on carefully engineered heuristics that incorporate strong problem-specific biases to navigate the enormous space of possible designs. In this work, we introduce a hierarchical reinfor