Back to the Future: Rethinking EDA Infrastructure for Agentic Systems in Chip Design Verification

Excerpt

arXiv:2610.06790v1 Announce Type: new Abstract: The unprecedented computational scale of modern artificial intelligence depends on complex, multi-billion-transistor Systems-on-Chip, yet the workflows that verify these chips remain stubbornly manual. Although Large Language Models (LLMs) have made rapid inroads into Electronic Design Automation (EDA), approximately 74.6% of existing studies target static Register-Transfer Level (RTL) code generation, leaving post-simulation verification and inter